1. Field of the Invention
The invention relates to data processing systems and more particularly to a method and apparatus for allowing indirect access to the registers and opcode specified by an instruction kept in a special alias register.
2. Description of the Related Art
The microprocessor described in the above-identified copending application Ser. No. 07/630,499, filed Dec. 20, 1990, can handle both Reduced Instruction Set Computer (RISC) instructions and Complex Instruction Set Computer (CISC) instructions. The mechanisms used to implement the CISC is substantially identical in format to that used to implement the user RISC instruction set and can execute at a sustained rate of two instructions per clock cycle from an on-chip ROM. To supply instructions at this rate the instruction decoder has two major design issues: (1) it must be able to get in and out of the microcode quickly without bubbles of inactivity in the pipeline, and (2) it must get quick access within the microcode routine to operands specified by the CISC instruction.
The first issue is solved by the invention described in Copending application Ser. No. 07/630,536 wherein an instruction decoder is described which includes an instruction sequencer with a microcode translation ROM for providing initial instructions in microcode flows and a mousetrap multiplexer having four inputs and an output. The a first input of the mousetrap multiplexer is connected to an instruction bus and a second input of the mousetrap multiplexer is connected to the microcode translation ROM. The output of the mousetrap multiplexer is connected to a machine bus. The mousetrap multiplexer includes means for selecting at its inputs from one of either the instruction bus, or microcode translation ROM, operand and opcode fields and for driving the selected operand and opcode fields onto the machine bus. This provides a superscaler architecture in that the machine can issue and execute more than one instruction per clock. It has the advantage that since the microinstructions of the microcode are virtually identical to the RISC macroinstructions, a permanent cache of routines is stored in on-chip ROM that would in RISC machines have to come from off-chip. It is possible to issue two instructions per clock, which eliminates the bus bandwidth problems that would exist if all that code had to be fetched from off-chip.
The second issue of providing quick access within the microcode routine to operands specified by the CISC instruction is the subject of the present invention.
It is therefore an object of this invention to provide a method of quick access within the microcode routine to operands specified by a CISC instruction.